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| IN74ACT158 QUAD 2-INPUT DATA SELECTOR/MULTIPLEXER High-Speed Silicon-Gate CMOS The IN74ACT158 is identical in pinout to the LS/ALS138, HC/HCT138. The IN74ACT158 may be used as a level converter for interfacing TTL or NMOS outputs to High Speed CMOS inputs. This device routes 2 nibbles (A or B) to a single port (Y) as determined by the Select input. The data is presented at the outputs in invertered form. A high level on the Output Enable input sets all four Y outputs to a high level. * TTL/NMOS Compatible Input Levels Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 4.5 to 5.5 V Low Input Current: 1.0 A; 0.1 A @ 25C Outputs Source/Sink 24 mA * * * * ORDERING INFORMATION IN74ACT158N Plastic IN74ACT158D SOIC TA = -40 to 85 C for all packages LOGIC DIAGRAM PIN ASSIGNMENT PIN 16 =VCC PIN 8 = GND FUNCTION TABLE Inputs Outputs Output Select Y0-Y3 Enable H X H L L A0-A3 L H B0-B3 X=don't care A0-A3,B0-B3=the levels of the respective Data-Word Inputs 1 IN74ACT158 MAXIMUM RATINGS* Symbol Parameter Value Unit VCC DC Supply Voltage (Referenced to GND) -0.5 to +7.0 V VIN DC Input Voltage (Referenced to GND) -0.5 to VCC +0.5 V VOUT DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V IIN DC Input Current, per Pin mA 20 IOUT DC Output Sink/Source Current, per Pin mA 50 ICC DC Supply Current, VCC and GND Pins mA 50 PD Power Dissipation in Still Air, Plastic DIP+ 750 mW SOIC Package+ 500 Tstg Storage Temperature -65 to +150 C 260 TL Lead Temperature, 1 mm from Case for 10 C Seconds (Plastic DIP or SOIC Package) * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/C from 65 to 125C SOIC Package: : - 7 mW/C from 65 to 125C RECOMMENDED OPERATING CONDITIONS Symbol Parameter VCC DC Supply Voltage (Referenced to GND) VIN, VOUT DC Input Voltage, Output Voltage (Referenced to GND) TJ Junction Temperature (PDIP) TA Operating Temperature, All Package Types IOH Output Current - High IOL Output Current - Low t r, tf Input Rise and Fall Time * VCC =4.5 V VCC =5.5 V (except Schmitt Inputs) * VIN from 0.8 V to 2.0 V Min 4.5 0 Max 5.5 VCC 140 +85 -24 24 10 8.0 Unit V V C C mA mA ns/V -40 0 0 This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND(VIN or VOUT)VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. 2 IN74ACT158 DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND) Guaranteed VCC Limits Symbol Parameter Test Conditions V 25 C -40C to 85C VIH Minimum High- VOUT=0.1 V or VCC-0.1 V 4.5 2.0 2.0 Level Input 5.5 2.0 2.0 Voltage VIL Maximum Low - VOUT=0.1 V or VCC-0.1 V 4.5 0.8 0.8 Level Input 5.5 0.8 0.8 Voltage VOH Minimum High- IOUT -50 A 4.5 4.4 4.4 Level Output 5.5 5.4 5.4 Voltage * VIN=VIH or VIL 3.76 3.86 IOH=-24 mA 4.5 4.76 4.86 5.5 IOH=-24 mA VOL Maximum Low- IOUT 50 A 4.5 0.1 0.1 Level Output 5.5 0.1 0.1 Voltage * VIN= VIH or VIL 0.44 0.36 IOL=24 mA 4.5 0.44 0.36 5.5 IOL=24 mA IIN Maximum Input VIN=VCC or GND 5.5 0.1 1.0 Leakage Current 5.5 1.5 Additional Max. VIN=VCC - 2.1 V ICCT ICC/Input VOLD=1.65 V Max IOLD +Minimum 5.5 75 Dynamic Output Current VOHD=3.85 V Min IOHD +Minimum 5.5 -75 Dynamic Output Current VIN=VCC or GND ICC Maximum 5.5 8.0 80 Quiescent Supply Current (per Package) * All outputs loaded; thresholds on input associated with output under test. +Maximum test duration 2.0 ms, one output loaded at a time. Unit V V V V A mA mA mA A 3 IN74ACT158 AC ELECTRICAL CHARACTERISTICS(VCC=5.0 V 10%, CL=50pF,Input tr=tf=3.0 ns) Guaranteed Limits Unit Symbol Parameter 25 C -40C to 85C Min Max Min Max tPLH Propagation Delay, Select to Output Y 2.5 9.5 2.0 11.0 ns (Figure 2) tPHL Propagation Delay, Select to Output Y 1.5 9.0 1.5 10.0 ns (Figure 2) tPLH Propagation Delay, Output Enable to 1.5 9.5 1.5 10.5 ns Output Y (Figure 3) tPHL Propagation Delay, Output Enable to 1.5 9.5 1.5 10.5 ns Output Y (Figure 3) tPLH Propagation Delay, Input A or B to Output 1.5 8.0 1.0 8.5 ns Y (Figure 1) tPHL Propagation Delay, Input A or B to Output 1.5 6.5 1.0 7.5 ns Y (Figure 1) CIN Maximum Input Capacitance 4.5 4.5 pF Typical @25C,VCC=5.0 V 45 CPD Power Dissipation Capacitance pF Figure 1. Switching Waveforms Figure 2. Switching Waveforms Figure 3. Switching Waveforms 4 IN74ACT158 EXPANDED LOGIC DIAGRAM A0 B0 A1 B1 A2 B2 A3 B3 OE SELECT Y0 Y1 Y2 Y3 5 |
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